The Professional Preparation section lists academic qualifications such as degrees and diplomas. Each record stores the degree, major, institution and year. The records can also be hidden from public view by checking the hide checkbox. Please click here for available slides.
The Research and Expertise section describes the areas in which you have expertise or are involved in research. Research Explorer's search engine indexes data in this field for keyword searches. Please click here for available slides.
Digital systems testability, SoC design & test issues, DFT methodologies, test synthesis, test data compression, fault modeling and testing of ultra high-speed SoCs, testing signal integrity in gigahertz interconnects.
Computer aided design including digital circuit design, optimization, RTL estimation, high-level synthesis and low power design methodologies.
VLSI system modeling/architecture, hardware description languages, parallel processing, sensor & body-area network architectures, special-purpose microprocessor design and packet processing architecture.
The Publications section lists any and all publications worked on. Research Explorer's search engine indexes data in this field for keyword searches. The category field is a user defined field where any number of categories can be created by the user to categorize publications. For example, publications can be categorized by the Journal that they appear in. Please click here for available slides.
M. Nourani, M. Tehranipoor and N. Ahmed, "Low-Transition Test Pattern Generation for BIST-Based Applications,'' in IEEE Transactions on Computers, vol. 57, no. 3, pp. 303-315, March 2008. Category: IEEE Transactions on Computers
A. Amirabadi, Y. Mortazavi, A. Afzali-Kusha and M. Nourani, "Clock Delayed Domino Logic with Efficient Variable Threshold Voltage Keeper,'' in IEEE Transactions on VLSI, vol. 15, no. 2, pp. 125-134, Feb. 2007. Category: IEEE Transactions on VLSI
M. Akhbarizadeh, M. Nourani, R. Panigrahy and S. Sharma, "A TCAM-Based Parallel Architecture for High-Speed Packet Forwarding,'' in IEEE Transactions on Computers, vol. 56, no. 1, pp. 58-72, Jan. 2007. Category: IEEE Transactions on Computers
A. Namazi and M. Nourani, ``Distributed Voting for Fault-Tolerant Nanoscale Systems,'' in Proceedings of International Conference on Computer Design (ICCD), (Lake Tahoe, CA), pp. 568-573, Oct. 2007. Category: ICCD
A. Broumandnia, J. Shanbehzadeh and M. Nourani, ``Segmentation of Printed Farsi/Arabic Words,'' in Proceedings of IEEE/ACS International Conference on Computer Systems and Applications (AICCSA'07), pp. 761-766, May 2007. Category: AICCSA
Presentations and Projects
The Presentations and Projects section lists anything that does not fit in the publication category such as conferences, seminars, invited talks, etc. Research Explorer's search engine indexes data in this field for keyword searches. Please click here for available slides.
Testing Signal Integrity in Gigahertz SoCs Department of Electrical & Computer Engineering, University of Texas at Austin, (Austin, TX), Sept. 26, 2003., November 16, 2007.
TCAM-Based Parallel Architectures for Packet Processing Invited Nerd Lunch Presentation, Cisco Systems, Inc., (San Jose, CA), Oct. 13, 2004.
Ripple-Precharge TCAM for Low-Power Applications Texas Instruments Inc., (Dallas, TX), Aug. 10, 2006.
Testing for Signal Integrity and Process Variations Texas Instruments Inc., (Dallas, TX), Aug. 4, 2004.
New Challenges in Testing High-Speed System-on-Chips Department of Computer Science & Engineering, University of North Texas, (Denton, TX), Feb. 16, 2005.
The Appointments section lists work experience including previous appointments. Research Explorer's search engine indexes data in this field for keyword searches. Please click here for available slides.
Dr. Mehrdad Nourani, assistant professor of electrical engineering at The University of Texas at Dallas (UTD), has been granted a Career Award from the National Science Foundation (NSF) for his work with Very Large Scale Integrated (VLSI) circuits, particularly focusing on self-testing methods for high-speed chip interconnects.
The award, worth more than $389,000 over the next five years, is part of the NSF’s Faculty Early Career Development program. The Career Award is the NSF’s most prestigious honor for junior faculty members and recognizes and supports the activities of the teachers and scholars who are most likely to become the academic leaders of the 21st century. Recipients are selected on the basis of creative early career development plans that effectively integrate research and education within the context of the mission of their respective institutions.
The VLSI chips Nourani researches essentially are microelectronic circuits with millions of tiny transistors. Such sophisticated chips, often referred to as System-on-Chip (SoC), are used in numerous applications - including computers, cars, airplanes and communication and robotic systems - to perform control and data processing functions.
A new behavioral data analysis system under development at UT Dallas focuses on identifying potential Internet threats, but it comes with a nice bonus.
Researchers say the basic idea behind the system – detecting worrisome deviations from normal activity and quickly providing an alert so that immediate measures can be taken – could have application in areas far beyond the Web, such as health-care monitoring.
“We proposed a novel platform that thoroughly analyzes network traffic behavior to identify potential internet threats,” said Dr. Mehrdad Nourani, an associate professor of electrical engineering in the University’s Erik Jonsson School of Engineering and Computer Science. “But it could have much broader application.”
The Additional Information section describes any other topics you wish to display on your profile that is not in another section. Research Explorer's search engine indexes data in this field for keyword searches. Please click here for available slides.
Best Paper Award at the IEEE International Conference on Computer Design, 2004.
Scalable Multi-Search per Cycle TCAM Architectures for High-Speed Routers (Sponsored by Cisco Systems ; 2004-2005).
Signal Integrity Fault Modeling and Testing in High-Speed SoCs (Sponsored by the National Science Foundation ; 2001-2006).
Router-on-Chip: A Port-Sliced Architecture for Terabit Packet Routing Processors (Sponsored the Clark Foundation Research Initiation Grant (2002-2003)
Energy Efficient VLSI Architectures for Communications and Signal Processing (Sponsored by the Texas Telecommunications Consortium ; 2000-2001)
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