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    Faculty Profile — Is this you? Login to edit.Last Modified Time: 11:11:30 PM Thu, 26 Aug 2010 
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Sam Shichijo
Research Professor-Electrical Engineering
Contact Address   800 West Campbell Rd, Richardson, TX 75080     Office MailstopMail Box: EC32, ECSN, Room No.: 4-3104 
Email Address  shichijo@utdallas.edu    Primary Phone Number 972-883-6152    Media Contact
 Professional Preparation
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 DegreeMajorInstitutionYear
 Ph.D.Electrical EngineeringUniversity of Illinoise at Urbana-Champaign1980
 M.S.Electrical EngineeringUniversity of Illinois at Urbana-Champaign1978
 B.S.E.E.Electronic EngineeringUniversity of Tokyo1976
Collapse Section Expand Section Research and Expertise
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Expertise

  • Semiconductor Device Physics
  • TCAD (Technology Computer Aided Design)
  • Analog and RF Devices
  • IC Process Integration
Collapse Section Expand Section Publications
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 2 3 4 Next>> 27>>  
  YearPublication  Type
2009
“Solving the requirement for analog transistors in advanced CMOS SoC technologies” K. Benaissa, , H. Shichijo, G. Baldwin, S. Liu, P. Srinivasan, F. Hou, B. Obradovic, S. Yu, H. Yang, S.Venkataraman, H. Lu, submitted to 2009 Symposium on VLSI Technology.
Other
2009
“Solving the requirement for analog transistors in advanced CMOS SoC technologies” K. Benaissa, , H. Shichijo, G. Baldwin, S. Liu, P. Srinivasan, F. Hou, B. Obradovic, S. Yu, H. Yang, S.Venkataraman, H. Lu, submitted to 2009 Symposium on VLSI Technology.
Peer reviewed
2008
"45nm Low-Power CMOS SoC Technology with Aggressive Reduction of Random Variation for SRAM and Analog Transistors"  S. Ekbote, K. Benaissa, B. Obradovic, S. Liu, H. Shichijo, F. Hou, T. Blythe, T. W. Houston, S. Martin, R. Taylor, A. Singh, H. Yang, G. Baldwin, Digest of Technical Papers, 2008 Symposium on VLSI Technology, pp.160-161
Category: VLSI Technology Symposium
Peer reviewed
2008
“45nm Low-Power CMOS SoC Technology with Aggressive Reduction of Random Variation for SRAM and Analog Transistors” S. Ekbote, K. Benaissa, B. Obradovic, S. Liu, H. Shichijo, F. Hou, T. Blythe, T. W. Houston, S. Martin, R. Taylor, A. Singh, H. Yang, G. Baldwin, Digest of Technical Papers, 2008 Symposium on VLSI Technology, pp.160-161.
Peer reviewed
2005
 "Device Device and Technology Evolution for Si-Based RF Integrated Circuits", H.B. Bennett, R. Brederlow, J. Costa, P.E. Cottrell, M. Huang, A. A. Immorlica, Jr. J.-E. Mueller, M. Racanelli, H. Shichijo, C.E. Weitzel, and B. Zhao, IEEE Transactions on Electron Devices, Volume 52,  Issue 7,  July 2005 Page(s):1235 - 1258.
Category: IEEE Trans. Electron Devices
Peer reviewed
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 Additional Information
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Professional Affiliations
Fellow, Institute of Electrical and Electronics Engineers (IEEE)

Patents Issued
  • 7,250,334 "Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode"
  • 6,764,892 "Device and method of low voltage SCR protection for high voltage failsafe ESD applications"
  • 6,753,202 "CMOS photodiode having reduced dark current and improved light sensitivity and responsivity"
  • 6,621,064 "CMOS photodiode having reduced dark current and improved light sensitivity and responsivity"
  • 6,576,959 "Device and method of low voltage SCR protection for high voltage failsafe ESD applications"
  • 6,548,874 "Higher voltage transistors for sub micron CMOS processes"
  • 6,512,280 "Integrated CMOS structure for gate-controlled buried photodiode"
  • 6,392,263 "Integrated structure for reduced leakage and improved fill-factor in CMOS pixel"
  • 6,303,420 "Integrated bipolar junction transistor for mixed signal circuits"
  • 5,959,308 "Epitaxial layer on a heterointerface"
  • 5,894,145 "Multiple substrate bias random access memory device"
  • 5,595,925 "Method for fabricating a multiple well structure for providing multiple substrate bias for DRAM device formed therein"
  • 5,290,719 "Method of making complementary heterostructure field effect transistors"
  • 5,238,869 "Method of forming an epitaxial layer on a heterointerface"
  • 5,214,298 "Complementary heterostructure field effect transistors"
  • 5,164,917 "Vertical one-transistor DRAM with enhanced capacitance and process for fabricating"
  • 5,065,132 "Programmable resistor and an array of the same"
  • 4,914,053 "Heteroepitaxial selective-area growth through insulator windows"
  • 4,910,164 "Method of making planarized heterostructures using selective epitaxial growth"
  • 4,713,678 "dRAM cell and method"
  • 4,545,034 "Contactless tite RAM"

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