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    Faculty Profile — Is this you? Login to edit.Last Modified Time: 01:35:28 PM Fri, 13 Nov 2009 
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Carl Matthew Sechen
Professor-Electrical Engineering
Office MailstopMail Box: EC33, Room No.: ECSN 4.902 
Email Address  carl.sechen@utdallas.edu    Primary Phone Number 972-883-4727    Media Contact
 Professional Preparation
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 DegreeMajorInstitutionYear
 Ph.D.Electrical EngineeringUniversity of California, Berkeley1987
 M.S.Electrical EngineeringMassachusetts Institute of Technology1977
 B.E.E.Electrical EngineeringUniversity of Minnesota1975
Collapse Section Expand Section Research and Expertise
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Research Interests
My research interests center primarily on the design and computer-aided design of integrated circuits. I have ongoing projects in high-speed, energy-efficient DSP block design, low-power (sub-threshold) highdefinition video decoder design, as well as area-efficient and reliable embedded DRAM and SRAM design. Another key research project is cell sizing/selection for global power minimization in digital integrated circuits, including leakage power control, as well as variational sensitivity reduction and yield enhancement. Cell library optimization is also addressed. I am also working on time-to-digital conversion, crystalfree high-precision oscillator design, and all-digital analog-to-digital converter design.
Collapse Section Expand Section Publications
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  YearPublication  Type
2007
S. Sun and C. Sechen, "Post-Layout Comparison of High Performance 64b Static Adders in Energy-Delay Space," Proc. IEEE Int. Conf. on Computer Design (ICCD), Lake Tahoe, CA, October 2007.
Category: ICCD
Conference paper
2007
M. Rahman, H. Tennakoon, and C. Sechen, "Optimal Area-versus-Delay Circuit Sizing Using Ex-tended Logical Effort", Proc. Austin Conf. on Integrated Circuits and Systems (ACISC), May 14-15, 2007, Austin, TX.
Category: ACISC
Conference paper
2007
K. H. Chong and C. Sechen, "64b Adder Using Self-Calibrating Differential Output Prediction Logic," submitted February 28, 2007 to: IEEE Journal of Solid-State Circuits.
Category: IEEE Journal of Solid-State Circuits
Magazine/newsletter articles
2007
M. Vujkovic, D. Wadkins and C. Sechen, "Accurate Post-Layout Power versus Delay Curve Genera-tion," submitted February 26, 2007 to: IEEE Trans. on Computer-Aided Design.
Category: IEEE Transactions on Computer-Aided Design
Magazine/newsletter articles
2007
Sheng Sun and C. Sechen, "Post-Layout Comparison of High Performance 64b Static Adders in En-ergy-Delay Space, submitted February 15, 2007 to: IEEE Transactions on VLSI Systems.
Category: IEEE Transactions on VLSI Systems
Magazine/newsletter articles
Collapse Section Expand Section Appointments
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DurationRankDepartment / SchoolCollege / OfficeUniversity / Company
08/15/2005-PresentProfessorDepartment of Electrical Engineering The University of Texas at Dallas
07/1999-08/14/2005Professor  University of Washington
07/1992-06/1999Associate Professor  University of Washington
07/1990-06/1992Associate Professor  Yale University
07/1986-06/1990Assistant Professor  Yale University
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 Additional Information
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Honors and Awards
  • Fellow, Institute of Electrical and Electronics Engineers, 2002
  • Outstanding Research Advisor Award, Department of Electrical Engineering, University of Washington, 2002
  • Best Project Award, NSF Center for the Design of Digital and Analog ICs (CDADIC), 2002
  • SRC Inventor's Recognition Award, Semiconductor Research Corporation, 2001
  • SRC Technical Excellence Award, Semiconductor Research Corporation, 1994
  • SRC Inventor's Recognition Award, Semiconductor Research Corporation, 1988

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