The Professional Preparation section lists academic qualifications such as degrees and diplomas. Each record stores the degree, major, institution and year. The records can also be hidden from public view by checking the hide checkbox. Please click here for available slides.
The Research and Expertise section describes the areas in which you have expertise or are involved in research. Research Explorer's search engine indexes data in this field for keyword searches. Please click here for available slides.
My research interests center primarily on the design and computer-aided design of integrated circuits. I have ongoing projects in high-speed, energy-efficient DSP block design, low-power (sub-threshold) highdefinition video decoder design, as well as area-efficient and reliable embedded DRAM and SRAM design. Another key research project is cell sizing/selection for global power minimization in digital integrated circuits, including leakage power control, as well as variational sensitivity reduction and yield enhancement. Cell library optimization is also addressed. I am also working on time-to-digital conversion, crystalfree high-precision oscillator design, and all-digital analog-to-digital converter design.
The Publications section lists any and all publications worked on. Research Explorer's search engine indexes data in this field for keyword searches. The category field is a user defined field where any number of categories can be created by the user to categorize publications. For example, publications can be categorized by the Journal that they appear in. Please click here for available slides.
S. Sun and C. Sechen, "Post-Layout Comparison of High Performance 64b Static Adders in Energy-Delay Space," Proc. IEEE Int. Conf. on Computer Design (ICCD), Lake Tahoe, CA, October 2007. Category: ICCD
M. Rahman, H. Tennakoon, and C. Sechen, "Optimal Area-versus-Delay Circuit Sizing Using Ex-tended Logical Effort", Proc. Austin Conf. on Integrated Circuits and Systems (ACISC), May 14-15, 2007, Austin, TX. Category: ACISC
K. H. Chong and C. Sechen, "64b Adder Using Self-Calibrating Differential Output Prediction Logic," submitted February 28, 2007 to: IEEE Journal of Solid-State Circuits. Category: IEEE Journal of Solid-State Circuits
M. Vujkovic, D. Wadkins and C. Sechen, "Accurate Post-Layout Power versus Delay Curve Genera-tion," submitted February 26, 2007 to: IEEE Trans. on Computer-Aided Design. Category: IEEE Transactions on Computer-Aided Design
Sheng Sun and C. Sechen, "Post-Layout Comparison of High Performance 64b Static Adders in En-ergy-Delay Space, submitted February 15, 2007 to: IEEE Transactions on VLSI Systems. Category: IEEE Transactions on VLSI Systems
The Appointments section lists work experience including previous appointments. Research Explorer's search engine indexes data in this field for keyword searches. Please click here for available slides.
The Additional Information section describes any other topics you wish to display on your profile that is not in another section. Research Explorer's search engine indexes data in this field for keyword searches. Please click here for available slides.
Fellow, Institute of Electrical and Electronics Engineers, 2002
Outstanding Research Advisor Award, Department of Electrical Engineering, University of Washington, 2002
Best Project Award, NSF Center for the Design of Digital and Analog ICs (CDADIC), 2002
SRC Inventor's Recognition Award, Semiconductor Research Corporation, 2001
SRC Technical Excellence Award, Semiconductor Research Corporation, 1994
SRC Inventor's Recognition Award, Semiconductor Research Corporation, 1988
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