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Yiorgos Makris
Associate Professor-Electrical Engineering, Department of
Office MailstopECSN, Room No.: 4.914 
Email Address    Primary Phone Number 972-883-4360    URL Web Link    Media Contact
 Professional Preparation
 PhDComputer EngineeringUniversity of California San Diego2001
 MSComputer EngineeringUniversity of California, San Diego1998
 DiplomaComputer Engineering and InformaticsUniversity of Patras, Greece1995
Collapse Section Expand Section Research and Expertise
Awards and Honors
  • IEEE Computer Society, Meritorious Service Award, Apr ’10
  • National Academy of Engineering (NAE) Frontiers of Engineering Symposium Participant, Sep ’07
  • IEEE Computer Society, Certificate of Appreciation, Oct ’06, Oct ’08
  • Sheffield Distinguished Teaching Award, Faculty of Engineering, May ’06 
  • Yale University, Junior Faculty Fellowship, Jan ’05 - Dec ’05 
  • Paul Moore Award for Developing Course “Semiconductors, Computers and Communications”, May ’03 ($10K)
  • Paul Moore Award for Developing Course “Digital Systems Testing And Design for Testability”, May ’01 ($11K)
  • INTEL Corp. Recognition Award, Sep ’96
  • UCSD School of Engineering Industrial Fellowsh
Collapse Section Expand Section Publications
 1  2  
  YearPublication  Type
Y. Jin, Y. Makris, “Hardware Trojans in Wireless Cryptographic Integrated Circuits,” Special issue of IEEE Design & Test of Computers (D&T) on Verifying Physical Trustworthiness of Integrated Circuits and Systems, vol. 27, no. 1, pp. 26-35, 2010
Peer reviewed
H-G. Stratigopoulos, P. Drineas, M. Slamani, Y. Makris, “RF Specification Test Compaction using Learning Machines,” IEEE Transactions on Very Large Scale Integration (T.VLSI), vol. 18, no. 6, pp. 1002-1006, 2010
Peer reviewed
N. Kupp, P. Drineas, M. Slamani, Y. Makris, “On Boosting the Accuracy of Non-RF to RF Correlation-Based Specification Test Compaction,” Journal of Electronic Testing Theory and Applications (JETTA), Springer, vol. 25, no. 6, pp. 309-321, 2009
Peer reviewed
S. Almukhaizim, F. Shi, E. Love, Y. Makris, “Soft Error Tolerance and Mitigation in Asynchronous Burst Mode Circuits,” IEEE Transactions on Very Large Scale Integration (T.VLSI), vol. 17, no. 7, pp. 869-882, 2009
Peer reviewed
F. Shi, Y. Makris, “Enhancing Simulation Accuracy through Advanced Hazard Detection in Asynchronous Circuits,” IEEE Transactions on Computers (T.COMP), vol. 58, no. 3, pp. 394-408, 2009
Peer reviewed
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